Lightweight Memory Tracing Mathias Payer*, Enrico Kravina, Thomas Gross Department of Computer Science ETH Zürich, Switzerland * now at UC Berkeley

Source URL: hexhive.github.io

• Computer architecture
• Computing
• Software
• X86 architecture
• X86
• Binary translation
• Just-in-time compilation
• 64-bit computing

Applying Amdahl’s Other Law to the data center D. Cohen

Source URL: www.mulix.org

• Computer architecture
• Computer memory
• Hypervisor
• I/O virtualization
• Cache
• Virtualization
• Storage area network
• CPU cache
• Hyper-V
• Memory hierarchy
• Logical partition
• Direct memory access

In her work, Katrin Sigurdardóttir explores the way physical structures and boundaries define our perception. Through unexpected shifts in scale, she examines distance and memory and their embodiments in architecture, c

Source URL: katrinsigurdardottir.info

ue talking about memory in architecture based on the artifact? Is memory a physical or mental reality? Is it material or immaterial? In architecture, when we speak about memory, we essentially speak of materialized memor

Source URL: www.mudot.org

Rules of Thumb in Data Engineering Jim Gray, Prashant Shenoy December 1999 Revised March 2000 Technical Report

Source URL: research.microsoft.com

• Computer architecture
• Computer memory
• Cache
• Memory management
• Computer storage media
• Computer data storage
• Disk storage
• Random-access memory
• Five-minute rule
• Paging
• Disk cache
• Locality of reference

Congestion Control for Large-Scale RDMA Deployments Yibo Zhu1,3 Haggai Eran2 Daniel Firestone1 Chuanxiong Guo1 Marina Lipshteyn1 Yehonatan Liron2 Jitendra Padhye1 Shachar Raindel2 Mohamad Haj Yahia2 Ming Zhang1 1

Source URL: conferences.sigcomm.org

• Computing
• Network performance
• Computer architecture
• Flow control
• Transmission Control Protocol
• RDMA over Converged Ethernet
• Remote direct memory access
• Throughput
• Head-of-line blocking
• Packet loss
• Transport layer
• Fluid queue

Appears in the proceedings of the 34th International Symposium on Microarchitecture (MICRO), Dec. 3-Dec. 5, 2001, Austin, Texas. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution Ravi Rajwar a

Source URL: pages.cs.wisc.edu

• Concurrency control
• Computing
• Computer architecture
• Test-and-set
• Transactional memory
• Non-blocking algorithm
• Synchronization
• Monitor
• Lock
• Linearizability
• Consistency model
• CPU cache

S CIEntIfIC ProgrAmmIng Editors: Konstantin Läufer,

Source URL: www.blosc.org

• Computing
• Computer memory
• Computer architecture
• Computer engineering
• Computer hardware
• Cache
• Parallel computing
• Central processing unit
• CPU cache
• Memory hierarchy
• Multi-core processor
• Locality of reference

Android Binder Android Interprocess Communication Thorsten Schreiber First Advisor: Juraj Somorovsky Second Advisor: Daniel Bußmeyer

Source URL: www.nds.rub.de

• Computing
• Software
• Computer architecture
• Concurrent computing
• Computing platforms
• Inter-process communication
• Cross-platform software
• Memory management
• Android
• Dalvik
• User space
• Kernel

Architecture-­‐level  Security  Issues     for  main  memory   Ali  Shafiee   Aganda   •  Replay-­‐A;ack  

Source URL: www.eng.utah.edu